1. Field of the Invention
The present invention relates to an all digital phase-locked loop (ADPLL) and, more particularly, to a time-to-digital converter capable of reducing power consumption, noise, and area so as to accommodate a mobile communications terminal whose performance standard is strictly defined, and an ADPLL having the same.
2. Description of the Related Art
A charge pump phase-locked loop (PLL) has been largely used to design the existing RF frequency synthesizer for multi-band mobile communications, and an analog circuit designing technique is integrated into the charge pump PLL.
Thus, due to analog circuit and analog signal characteristics of the charge pump PLL, the charge pump PLL requires an analog/RF library in addition to design libraries provided by a standard digital CMOS process, so it is difficult to integrate the charge pump PLL together with a digital baseband signal processing block using a digital CMOS process.
In addition, the recent advancement of process techniques has emerged from the development of a nanometer digital CMOS process, which was prompted by rapidly developing digital baseband signal processing blocks.
In line with the progress in the development of nano-technology, digital circuits are being easily adapted to processing technologies desired to be manufactured and implemented, rather than being re-designed; however, an analog/RF circuit must be re-designed each time a process technology changes, and as CMOS processing technology advances toward the nano-scale, operational voltage is disadvantageously reduced.
Thus, because a large amount of time and expenses are required to improve the problems arising in designing an analog/RF integrated circuit according to the nano-class digital CMOS process, research and development into a digital RF is actively ongoing in an effort to digitalize an analog/RF circuit block.
In particular, a frequency synthesizer of an RF transceiver is part that can be fully digitalized. The technique of the digital PLL frequency synthesizer is a long-established technique, but because the digital PLL frequency synthesizer has phase noise and undesirable jitter characteristics, it has not been widely used as a local oscillator of a mobile communications RF transceiver requiring high quality phase noise.
However, recently, a novel type of all digital PLL (ADPLL) has been developed by applying a digital PLL technique to a mobile communications frequency synthesizer. The difference between the conventional digital PLL and the ADPLL lies in a digitally controlled oscillator (DCO). Namely, the conventional DCO is implemented through the use of a digital logic, while today's DCO is implemented through the use of an LC resonator.
Thus, the LC resonance DCO has excellent characteristics in terms of phase noise or jitter noise compared with the conventional digital logic.
The LC resonance DCO adjusts an oscillation frequency by controlling a fine variation of capacitance within the LC resonator, so a capacitor bank is divided into a coarse adjustment bank and a fine adjustment bank. The coarse adjustment bank of the DCO is used to quickly trace a PLL for the purpose of a desired PLL frequency, and when the target PLL frequency is approached by the coarse adjustment bank, the fine adjustment bank follows according to a mode conversion signal to lock on to the target PLL frequency through fine tracking.
A fine phase error (ε) used for fine tracking is generated by a time-to-digital converter (TDC), and a fine phase difference between a reference clock and a DCO clock is compensated for by an arithmetic operation phase detector according to the fine phase error (ε).
The phase noise performance of the existing digital PLL is determined by the resolution of the fine phase error (ε) that can be detected by the TDC. Namely, in the case that the resolution of the fine phase error detected by the TDC (or the fine phase error detection resolution) is high, phase noise is improved, and the fine phase error detection resolution is determined by a minimum delay time of a delay element of an inverter chain constituting the TDC.
However, the inverter chain of the related art TDC is operated by using a DCO clock having a high frequency, causing excessive noise and much power consumption.
Also, as mentioned above, the existing DCO is divided into the coarse adjustment bank and the fine adjustment bank, so when the digital PLL is locked in a coarse locking mode, a lock indication signal is required for changing from the coarse adjustment bank of the DCO to the fine adjustment bank and, at this time, a lock detector is used.
A great number of lock detectors have been developed for the existing analog PLL, but not for the digital PLL, and in general, a look-up table which generally uses a memory and has a complicated structure is used.
In addition, the structure of the related art ADPLL is such that it uses narrowband, so it is difficult to use in other application fields using a broader bandwidth.